This invention is in the field of solid-state memory. Embodiments of this invention are more specifically directed to static random access memory (SRAM) cells and devices.
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. The computational power of these modern devices and systems is typically provided by one or more processor “cores”. These processor cores operate as a digital computer, in general retrieving executable instructions from memory, performing arithmetic and logical operations on digital data retrieved from memory, and storing the results of those operations in memory. Other input and output functions for acquiring and outputting the data processed by the processor cores are performed as appropriate. Considering the large amount of digital data often involved in performing the complex functions of these modern devices, significant solid-state memory capacity is now commonly implemented in the electronic circuitry for these systems.
Static random access memory (SRAM) has become the memory technology of choice for much of the solid-state data storage requirements in these modern power-conscious electronic systems. As is fundamental in the art, SRAM cells store contents “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory; this is in contrast to “dynamic” RAM (“DRAM”), in which the data must be periodically refreshed in order to be retained.
Advances in semiconductor technology in recent years have enabled the shrinking of minimum device feature sizes (e.g., MOS transistor gates) into the sub-micron range. This miniaturization is especially beneficial when applied to memory arrays, because of the large proportion of the overall chip area often devoted to on-chip memories. As a result, significant memory resources are now often integrated as embedded memory into larger-scale integrated circuits, such as microprocessors, digital signal processors, and “system-on-a-chip” integrated circuits. However, this physical scaling of device sizes raises significant issues, especially in connection with embedded SRAM but also in SRAM realized as “stand-alone” memory integrated circuit devices. Several of these issues are due to increased variability in the electrical characteristics of transistors formed at these extremely small feature sizes. This variability in characteristics has been observed to increase the likelihood of read and write functional failures, on a cell-to-cell basis. Sensitivity to device variability is especially high in those memories that are at or near their circuit design limits. The combination of increased device variability with the larger number of memory cells (and thus transistors) within an integrated circuit renders a high likelihood that one or more cells cannot be read or written as expected.
An example of a conventional SRAM cell is shown in FIG. 1a. In this example, SRAM cell 12 is a conventional six-transistor (6-T) static memory cell 12, which in this case is in the jth row and kth column of a memory array. SRAM memory cell 12 is biased between the voltage on power supply line Vdda and a ground reference voltage Vssa. SRAM memory cell 12 is constructed in the conventional manner as a pair of cross-coupled CMOS inverters, one inverter of series-connected p-channel load transistor 13a and n-channel driver transistor 14a, and the other inverter of series-connected p-channel load transistor 13b and n-channel transistor 14b; the gates of the transistors in each inverter are connected together and to the common drain node of the transistors in the other inverter, in the usual manner. The common drain node of transistors 13a, 14a constitutes storage node SNT, and the common drain node of transistors 13b, 14b constitutes storage node SNB, in this example. N-channel pass transistor 15a has its source/drain path connected between storage node SNT and bit line BLTk for the kth column, and n-channel pass transistor 15b has its source/drain path connected between storage node SNB and bit line BLBk. The gates of pass transistors 15a, 15b are driven by word line WLj for this jth row in which cell 12 resides.
In operation, bit lines BLTk, BLBk are typically precharged to a high voltage (at or near power supply voltage Vdda), and are equalized to the same voltage at the beginning of both read and write cycles, after which bit lines BLTk, BLBk then float at that precharged voltage. To access cell 12 for a read operation, word line WLj is then energized, turning on pass transistors 15a, 15b, and connecting storage nodes SNT, SNB to the then-floating precharged bit lines BLTk, BLBk. The differential voltage developed on bit lines BLTk, BLBk is then sensed and amplified by a sense amplifier. In a write operation, typical modern SRAM memories include write circuitry that pulls one of then-floating precharged bit lines BLTk, BLBk low (i.e., to a voltage at or near ground voltage Vssa) depending on the data state to be written. Upon word line WLj then being energized, the low level bit line BLTk or BLBk will pull down its associated storage node SNT, SNB, causing the cross-coupled inverters of addressed cell 12 to latch in the desired state.
As mentioned above, device variability can cause read and write failures, particularly in memory cells constructed with sub-micron minimum feature size transistors. A write failure occurs when an addressed SRAM cell does not change its stored state when written with the opposite data state. Typically, this failure has been observed to be due to the inability of write circuitry to pull down the storage node currently latched to a high voltage. For example, in an attempt to write a low logic level to storage node SNT, if bit line BLTk is unable to sufficiently discharge storage node SNT to trip the inverter of transistors 13b and 14b, cell 12 may not latch to the desired data state.
Cell stability failures are the converse of write failures—a write failure occurs if a cell is too stubborn in changing its state, while a cell stability failure occurs if a cell changes its state too easily, such as may occur to an unselected cell during a write to a cell in its same row. More specifically, an unselected cell in a selected row is commonly referred to as a “half-selected” cell, as will now be described in connection with FIG. 1b. 
FIG. 1b illustrates an example of a conventional interleaved array 20 of SRAM cells 12, each cell 12 constructed in the manner described relative to FIG. 1a. A pair of bit lines are shared by each column of SRAM cells 12, and extend between precharge/equalization circuitry 22 and column select multiplexers 24, with SRAM cells 12 in that column connected to those bit lines in the manner described above relative to FIG. 1a. SRAM cells 12 are also arranged in rows, with each row of cells 12 sharing one of word lines WL0 through WL3. One of word lines WL0 through WL3 is driven active by a row decoder and word line driver (not shown), in response to a row address value.
Array 20 in this example includes sixty-four SRAM cells 12, in four rows and sixteen columns. This architecture is referred to as interleaved, in that the columns are grouped such that the addressing of a data word selects one column in each group of columns, along the selected row. In this example, the groups are of four columns each, such that a given column address value selects one column from each group. This interleaving is accomplished, in this conventional architecture, by column select multiplexers 240 through 243, each associated with four adjacent columns of cells 12. Each of column select multiplexers 240 through 243 select one column from its group of four in response to the state of the least significant two column address bits CS[1:0], as applied by column decode circuitry (not shown). The columns selected by column select multiplexers 240 through 243 are placed in communication with a respective one of read/write circuits 250 through 253. In this architecture, each read/write circuit 250 through 253 is connected to a corresponding input/output line D/Q0 through D/Q3, respectively, as shown.
FIG. 1b illustrates an example of a write cycle being applied to four SRAM cells 12[SEL] in array 20. In this example, selected SRAM cells 12[SEL] are in the row associated with word line WL1, and reside in the fourth column in each of the four groups of columns associated with corresponding read/write circuits 250 through 253 (i.e., column address bits CS[1:0] both carry a “1” logic level). Other cells 12[HS] that are in the same row as selected SRAM cells 12[SEL], but that are in the unselected columns, are referred to as “half-selected”. During a write to selected SRAM cells 12[SEL], pass transistors 15a, 15b (FIG. 1a) for each of these half-selected cells 12[HS] will also be turned on by word line WL1, connecting their respective storage nodes SNT, SNB to the unselected bit lines BLT, BLB. However, because these columns are not selected for the write cycle, neither of those bit lines BLT, BLB for the half-selected columns will be driven low by read/write circuit 25, but will be floating at their precharged voltage. In effect, these half-selected cells 12[HS] will be in the same state as during a read cycle, in which the levels at those storage nodes SNT, SNB will drive the capacitive load presented by the corresponding bit lines BLT, BLB.
It has been observed that this half-selection can upset the stored state of half-selected cells 12[HS]. Noise of sufficient magnitude coupling to the bit lines of the half-selected columns, during a write to the selected columns in the same row, can cause a false write of data to those half-selected columns. In effect, such write cycle noise can be of sufficient magnitude as to trip the inverters of one or more of the half-selected cells 12[HS]. The possibility of such stability failure is exacerbated by device mismatch and variability, as discussed above.
In conventional SRAM cells such as 6-T SRAM cell 12 of FIG. 1a, the designer is therefore faced with a tradeoff between cell stability on one hand, and write margin on the other. In a general sense, cell stability is favored by pass transistors 15a, 15b having relatively weak drive as compared with load transistors 13 and driver transistors 14, because this results in weak coupling between the bit lines and storage nodes and relatively strong drive of the latched state at storage nodes SNT, SNB. Conversely, write margin is favored by pass transistors 15a, 15b having relatively strong drive as compared with load transistors 13 and driver transistors 14, because this enables strong coupling between the bit lines and storage nodes, resulting in storage nodes SNT, SNB having weak resistance to changing state. Accordingly, the design of conventional 6-T SRAM cells 12 involves a tradeoff between these two vulnerabilities.
Unfortunately, the design window in which both adequate cell stability and adequate write margin can be attained is becoming smaller with continued scaling-down of device feature sizes, for the reasons mentioned above. In addition, it has been observed that the relative drive capability of p-channel MOS transistors relative to re-channel MOS transistors is increasing as device feature sizes continue to shrink, which skews the design window toward cell stability over write margin.
One conventional approach toward relaxing these ever-tightening design constraints is known in the art as “write-assist”. According to this approach, the power supply bias applied to SRAM cells (e.g., power supply voltage Vdda of FIG. 1) in write cycles is reduced, or disconnected so as to float. Conventional write-assist circuitry includes a power switch associated with each column of an array, or in some cases associated with multiple columns. Floating write assist bias in write cycles is attained by the power switch disconnecting cells in the selected column from the power supply voltage. In one approach, reduced voltage write assist bias turns off, in write cycles, a power switch that is connected in parallel with a diode-connected transistor between the memory cells and the power supply voltage. The cell bias in the selected column is thus at least a diode voltage drop from the full power supply voltage, during write cycles. For either reduced or floating write assist bias, the drive of the load and driver transistors in the SRAM cell is reduced relative to the drive of the pass transistors, making it easier for the low level bit line to flip the state of the addressed cell.
Another conventional approach addressing the shrinking design window to satisfy both cell stability and write margin constraints is the construction of high performance SRAM memories using eight transistor (“8-T”) memory cells. As known in the art, the 8-T SRAM cell consists of a 6-T latch as shown in FIG. 1a, in combination with a two-transistor read buffer. Each cell receives separate read and write word lines and separate read and write bit lines. The complementary write bit lines are selectively coupled to the storage nodes of the 6-T latch by the pass transistors gated by the write word line, as in the conventional 6-T SRAM cell. The read buffer includes the series connection of a drive transistor gated by one of the storage nodes and a pass transistor gated by the read word line, connected between a reference voltage (e.g., ground) and the read bit line. In this 8-T construction, the pass transistors involved in the write cycle can have strong drive to provide good write margin, without affecting cell stability during read operations (because those pass transistors remain off). However, in an interleaved architecture, half-selected cells in a write cycle (i.e., cells in the selected row that are not being written) can still exhibit cell instability, because the write word line will be energized in that situation. To avoid this situation, the 8-T cells are implemented in a non-interleaved architecture, in which the entire selected row of cells is written in a write cycle. As known in the art, non-interleaved memory arrays are vulnerable to multiple-bit soft error failures, and consume additional chip area. In addition, these conventional 8-T cells source a single-ended read, rather than the differential signal sourced by the 6-T cell; either the read signal is reduced as a result, or the device sizes for the read buffer must be increased to compensate for that weaker signal.
By way of further background, my copending and commonly assigned U.S. patent application Ser. No. 12/827,706, filed Jun. 24, 2010, entitled “Bit-by-Bit Write Assist for Solid-State Memory”, describes a solid-state memory in which write assist circuitry is implemented within each memory cell. As described in this application, each memory cell includes a pair of power switch transistors that selectably apply bias (either power supply voltage Vdd or ground) to the inverters of the memory cell. One of the power switch transistors is gated by a word line indicating selection of the row containing the cell, and the other is gated by a column select signal indicating selection of the column containing the cell in a write cycle. Upon a write to the cell, both power switch transistors are turned off, removing bias from the inverter. With bias removed from the inverters, the writing of an opposite cell state is facilitated.
By way of further background, my copending and commonly assigned U.S. patent application Ser. No. 12/834,914, filed Jul. 13, 2010, entitled “Memory Cell with Equalization Write Assist Solid-State Memory”, describes a solid-state memory in which equalization transistors are included within each memory cell. In each selected memory cell in a write cycle, those equalization transistors are turned on to short the storage nodes to one another. The bit line driven by the write circuitry can then more readily define the state of the cross-coupled inverters, by eliminating the tendency of those inverters to maintain the previously stored latch state.
By way of further background, Takeda et al., “A Read-Static-Noise-Margin-Free SRAM Cell for Low-VDD and High-Speed Applications”, J. Solid-State Circuits, Vol. 41, No. 1 (IEEE, January 2006), pp. 113-21, describes a seven-transistor (7-T) SRAM cell in which an additional transistor is included in series with one of the inverters, and is gated by the word line. The inverter that includes the extra series transistor has its common drain node coupled to its bit line only in write cycles (i.e., by a “write word line”); the opposing inverter drives its bit line in read cycles. This single-ended read limits the number of cells that can connect to the same bit line, because of the reduced read signal strength. The chip area efficiency is thus impacted by that constraint, and also because of the three separate word lines that must now be routed to each cell. In addition, the asymmetric layout of the 7-T cell precludes implementation in an interleaved array architecture, increasing the likelihood of multiple-bit soft errors, and further reducing chip area efficiency.